FIG. 1 (Prior Art) is a diagram of a phase leg involving two Insulated Gate Bipolar Transistors (IGBTs) T1 and T2, two power diodes D1 and D2, two gate drivers 1 and 2, gate resistors 3-6 and diodes 7 and 8. The inductor symbol 9 represents a large inductive load. The inductor symbol 10 represents inductance in the power supply and ground lines. FIG. 2A (Prior Art) is a waveform diagram of voltages and currents in the circuit of FIG. 1 for a situation in which the load current ILOAD is positive. FIG. 2B (Prior Art) is a waveform diagram for a situation in which the load current ILOAD is negative. The gate resistors are provided to slow down the turn on and the turn off of the IGBTs.
Assume first a condition in which T1 is off. Current is flowing from node 11, through the low-side power diode D2, to node 12, and out through inductive load 9. At time t1, the gate signal G1 transitions from low to high. At time t2, T1 begins to conduct current. As the current IT1 increases, the diode current ID2 in the low-side power diode D2 decreases. Diode D2 then goes into reverse recovery. This reverse recovery is evidenced in a current undershoot 13. If the dI/dt change in diode current ID2 through diode D2 is too large during this time, then diode D2 can be damaged or may fail. To avoid this, gate resistor 3 is provided. Gate resistor 3 increases the resistance between the driver 1 and the gate of T1. The gate resistor limits dI/dt through T1 when T1 is turning on, and therefore also limits dI/dt in the diode D2 between times t2 and t3. Starting at time t3, which is approximately when reverse recovery peak 13 is at its maximum, the voltage VT1 across transistor T1 can change. From time t3 to time t4, the voltage across T1 decreases. The rate of this voltage decrease is dV/dt. In many modern IGBT devices, the influence of the gate resistance on this dV/dt across the IGBT is weak. Increasing the gate resistance has only a slight effect in decreasing the dV/dt. In high voltage phase legs, a large dV/dt can cause problems such as EMI problems. Other devices on the printed circuit board can also be adversely affected by the high dV/dt. A larger gate resistance may be provided to reduce the dV/dt to acceptable levels, but then the dI/dt of the transistor at turn on between times t2 and t3 is lower than it otherwise could be. Turning on transistor T1 with too small of an dI/dt generally results in switching losses. If the increased switching losses cannot be tolerated, then a smaller gate resistance is used and other possibly expensive and cumbersome techniques are applied to deal with the dV/dt problem.
When an IGBT in a phase leg is turned off, there is also a change in voltage across the transistor and a change in current. In the circuit of FIG. 1, assume transistor T1 is conducting. Current is flowing from node 14, through T1, to node 12, and out through the inductive load 9. Then at time t5 the gate signal G1 transitions from high to low. When the gate signal G1 transitions low, the transistor T1 does not actually turn off immediately. It takes time within the transistor for the gate to be discharged to the point that the gate voltage reaches the threshold voltage. Once the voltage on the gate decreases below the threshold voltage, then the resistance through the IGBT increases. Due to current flow through T1, the voltage drop across the transistor increases. At time t6, the voltage VT1 across T1 in FIG. 2A increases. When voltage crosses the supply voltage VDC at time t7, current begins to commutate to diode D2. The current IT1 drops and the current ID2 increases resulting in a voltage overshoot of the supply voltage VDC and VT1. Reference numeral 15 identifies this voltage overshoot. This is manifest as a negative dI/dt in the IT1 waveform. A circuit designer may want to wave shape this falling signal edge of the IT1 current, but the influence of the gate resistance on this dI/dt of transistor turn off is small. A very large gate resistance that is large enough to slow this negative dI/dt cannot generally be used, because such a large gate resistance might increase the delay period between times t5 and t6 too much.
The phase leg circuit of FIG. 1 includes a common gate resistance circuit involving a resistor and a parallel path of a resistor and a series diode. This gate resistance circuit provides a first gate resistance for turn on and a second gate resistance for turn off. In transistor turn off situations, where the gate driver 1 is outputting a low voltage as compared to the higher voltage on the gate of T1, diode 7 is forward biased. The effective resistance between the gate driver 1 and the gate of transistor T1 is the parallel combination of the resistances of resistors 3 and 4. In transistor turn on situations, where the gate driver 1 is outputting a high voltage as compared to the lower voltage on the gate of T1, diode 7 is reverse biased. The effective resistance between the gate driver 1 and the gate of transistor T1 is the resistance of resistor 3. This gate resistance circuit allows different turn on and turn off gate resistances to be used.